Korea Advanced Institute of Science and Technology (KAIST, President Lee Kwang-hyeong) announced on the ninth that a research team led by Professor Jeongwon Kim of the Department of Mechanical Engineering developed a technology that may generate and distribute ultra-low-noise clock signals inside a semiconductor chip using lasers.
Previously, the accuracy of the clock signal was normally at the extent of picoseconds (1/1 trillionth of a second), but with the technology developed this time, a clock with accurate timing at the extent of femtosecond (1/one thousandth of a second) is superior to the prevailing method. It’s explained that signals could be generated and distributed throughout the chip, and the warmth generated within the chip through the clock distribution process could be drastically reduced.
KAIST Department of Mechanical Engineering Ph.D. student Minji Hyun participated as the primary creator and this paper, which was a joint research with Professor Ha-Yeon Jung of Korea University Sejong Campus, was published within the international journal Nature Communications on April twenty fourth.
In an effort to distribute clock signals inside a high-performance semiconductor chip, numerous clock drivers should be utilized in a clock distribution network (CDN), which not only increases heat generation and power consumption but in addition affects clock timing. will fall Clock timing inside a chip is decided by jitter, which changes rapidly at random, and skew, which is the difference between clock arrival times between different points throughout the chip. Because the variety of clock drivers increases, each jitter and skew It often grows to greater than a couple of picoseconds.
To unravel this problem, the research team introduced a recent clock distribution network technology that uses an optical frequency comb laser with sub-femtosecond jitter because the master clock. It is a clock signal in the shape of a square wave through the strategy of charging and discharging the clock distribution network in the shape of a metal structure within the semiconductor chip after converting the optical pulses generated from the optical frequency comb laser into photocurrent pulses using a high-speed photodiode. method to create.
Particularly, with this technology, clocks could be distributed inside a chip through only a metal structure that removes the clock drivers of the clock distribution network, thereby improving timing performance and significantly reducing heat generation throughout the chip. Consequently, it was possible to point out excellent timing performance by lowering jitter and skew to lower than 20 femtoseconds, which is 1/100 of the previous method, and power consumption and warmth generation through the clock distribution process throughout the chip is also reduced to 1/100 of the previous method. told
Professor Jeongwon Kim said, “Currently, we’re conducting research on improving performance by supplying a sampling clock signal with very low jitter to high-speed circuits resembling analog-to-digital converters.” A follow-up study can also be being planned.”
Meanwhile, this research was conducted with the support of the Samsung Future Technology Development Center.
Reporter Yeju Cho joyejuoffice@aitimes.com
