The electronics industry is approaching a limit to the variety of transistors that might be packed onto the surface of a pc chip. So, chip manufacturers want to construct up fairly than out.
As a substitute of compressing ever-smaller transistors onto a single surface, the industry is aiming to stack multiple surfaces of transistors and semiconducting elements — akin to turning a ranch house right into a high-rise. Such multilayered chips could handle exponentially more data and perform many more complex functions than today’s electronics.
A major hurdle, nonetheless, is the platform on which chips are built. Today, bulky silicon wafers serve because the primary scaffold on which high-quality, single-crystalline semiconducting elements are grown. Any stackable chip would need to include thick silicon “flooring” as a part of each layer, slowing down any communication between functional semiconducting layers.
Now, MIT engineers have found a way around this hurdle, with a multilayered chip design that doesn’t require any silicon wafer substrates and works at temperatures low enough to preserve the underlying layer’s circuitry.
In a study appearing today within the journal , the team reports using the brand new method to fabricate a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of one another.
The strategy enables engineers to construct high-performance transistors and memory and logic elements on any random crystalline surface — not only on the bulky crystal scaffold of silicon wafers. Without these thick silicon substrates, multiple semiconducting layers might be in additional direct contact, leading to raised and faster communication and computation between layers, the researchers say.
The researchers envision that the tactic may very well be used to construct AI hardware, in the shape of stacked chips for laptops or wearable devices, that will be as fast and powerful as today’s supercomputers and will store huge amounts of knowledge on par with physical data centers.
“This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says study writer Jeehwan Kim, associate professor of mechanical engineering at MIT. “This may lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.”
The study’s MIT co-authors include first writer Ki Seok Kim, Seunghwan Search engine marketing, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, together with collaborators from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.
Seed pockets
In 2023, Kim’s group reported that they developed a way to grow high-quality semiconducting materials on amorphous surfaces, much like the various topography of semiconducting circuitry on finished chips. The fabric that they grew was a sort of 2D material referred to as transition-metal dichalcogenides, or TMDs, considered a promising successor to silicon for fabricating smaller, high-performance transistors. Such 2D materials can maintain their semiconducting properties even at scales as small as a single atom, whereas silicon’s performance sharply degrades.
Of their previous work, the team grew TMDs on silicon wafers with amorphous coatings, in addition to over existing TMDs. To encourage atoms to rearrange themselves into high-quality single-crystalline form, fairly than in random, polycrystalline disorder, Kim and his colleagues first covered a silicon wafer in a really thin film, or “mask” of silicon dioxide, which they patterned with tiny openings, or pockets. They then flowed a gas of atoms over the mask and located that atoms settled into the pockets as “seeds.” The pockets confined the seeds to grow in regular, single-crystalline patterns.
But on the time, the tactic only worked at around 900 degrees Celsius.
“You have got to grow this single-crystalline material below 400 Celsius, otherwise the underlying circuitry is totally cooked and ruined,” Kim says. “So, our homework was, we needed to do an analogous technique at temperatures lower than 400 Celsius. If we could do this, the impact could be substantial.”
Increase
Of their recent work, Kim and his colleagues looked to fine-tune their method so as to grow single-crystalline 2D materials at temperatures low enough to preserve any underlying circuitry. They found a surprisingly easy solution in metallurgy — the science and craft of metal production. When metallurgists pour molten metal right into a mold, the liquid slowly “nucleates,” or forms grains that grow and merge right into a commonly patterned crystal that hardens into solid form. Metallurgists have found that this nucleation occurs most readily at the sides of a mold into which liquid metal is poured.
“It’s known that nucleating at the sides requires less energy — and warmth,” Kim says. “So we borrowed this idea from metallurgy to utilize for future AI hardware.”
The team looked to grow single-crystalline TMDs on a silicon wafer that already has been fabricated with transistor circuitry. They first covered the circuitry with a mask of silicon dioxide, just as of their previous work. They then deposited “seeds” of TMD at the sides of every of the mask’s pockets and located that these edge seeds grew into single-crystalline material at temperatures as little as 380 degrees Celsius, in comparison with seeds that began growing in the middle, away from the sides of every pocket, which required higher temperatures to form single-crystalline material.
Going a step further, the researchers used the brand new method to fabricate a multilayered chip with alternating layers of two different TMDs — molybdenum disulfide, a promising material candidate for fabricating n-type transistors; and tungsten diselenide, a cloth that has potential for being made into p-type transistors. Each p- and n-type transistors are the electronic constructing blocks for carrying out any logic operation. The team was capable of grow each materials in single-crystalline form, directly on top of one another, without requiring any intermediate silicon wafers. Kim says the tactic will effectively double the density of a chip’s semiconducting elements, and particularly, metal-oxide semiconductor (CMOS), which is a basic constructing block of a contemporary logic circuitry.
“A product realized by our technique will not be only a 3D logic chip but additionally 3D memory and their mixtures,” Kim says. “With our growth-based monolithic 3D method, you can grow tens to a whole bunch of logic and memory layers, right on top of one another, and they might give you the option to speak thoroughly.”
“Conventional 3D chips have been fabricated with silicon wafers in-between, by drilling holes through the wafer — a process which limits the variety of stacked layers, vertical alignment resolution, and yields,” first writer Kiseok Kim adds. “Our growth-based method addresses all of those issues directly.”
To commercialize their stackable chip design further, Kim has recently spun off an organization, FS2 (Future Semiconductor 2D materials).
“We thus far show an idea at a small-scale device arrays,” he says. “The following step is scaling up to indicate skilled AI chip operation.”
This research is supported, partially, by Samsung Advanced Institute of Technology and the U.S. Air Force Office of Scientific Research.
